Shail Dave

Grad Service Assistant, Sch Compt & Augmented Intellig

shail.dave@asu.edu

Mail code: 8809

Campus: Tempe
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Student Information

Graduate Student
Computer Engineering (Computer Systems)
Ira A Fulton Engineering

Long Bio

Shail Dave is a final-year Ph.D. candidate, majoring in Computer Engineering, at the School of Computing and Augmented Intelligence (SCAI) since 2017. Before joining the doctoral program, he earned a master's at ASU in Computer Engineering in 2016. He is currently affiliated with Compiler Microarchitecture Lab / Make Programming Simple Lab and Center for Embedded Systems, working with Prof. Aviral Shrivastava on "Agile and Sustainable, Accelerated Computing".

Shail's research techniques and infrastructures enable the efficient processing of critical applications such as machine/deep learning on hardware accelerators in an agile and sustainable manner. More specifically, his research develops compilation and mapping optimizations for accelerators, execution cost modeling and bottleneck characterization of accelerators, language for automated accelerator designs, efficient dense/sparse tensor computations, accelerator simulators, and exploration of hardware/software codesigns through systematic heuristics and machine learning. His research is regularly published in and referred by the top ACM/IEEE conferences and journals in these domains (design automation, embedded systems, and computer architecture). His research has also been featured in premier forums (ARM Research Summits, Annual Days of NSF/Intel CAPA Research Center, Future Chips Forum, etc.). Read more about his vision paper on "Accelerator Design 2.0" here (Summary Talk) and a comprehensive literature survey on machine learning accelerator systems here. His research and vision has directly contributed to development and participation in highly competitive national projects and such project proposals (including projects funded by Semiconductor Resarch Association's AI Hardware program, NSF/Intel CAPA center) and a new topical course at ASU (on Topics in Machine Learning Accelerator Design).

Shail's industry experiences include compiler optimizations for wide-scale commodity embedded systems, as well as digital design and verification for FPGA-based accelerators and ASICs. He is also experienced in piloting novel research projects and infrastructures, both in collaboration with expert industry/academic researchers and internships (Intel Parallel Computing Lab, ARM Research, MathWorks Research, Space Application Center–ISRO), especially for cutting-edge accelerator design and system stack development.

Shail is a recipient of several competitive honors and awards. He also regularly serves in various professional and community activities, including reviewing for top ACM/IEEE conferences and journals in his research areas (DAC, ESWEEK, RTSS, Sensors, TECS, TODAES), the program or organizing committee for these top conferences and workshops (ESWEEK, ASPLOS-LATTE), and various mentorship programs and activities.

Education

Ph.D. Candidate, School of Computing and AI, Ira A. Fulton Schools of Engineering, ASU - 2017-Present
Master of Science, Computer Engineering, Arizona State University, 2016
Bachelors of Engineering, Electronics and Communication Engineering, L. D. College of Engineering, Ahmedabad 2014

Curriculum Vitae

Images

machine-learning-accelerators.png

Video

Research Website URL

https://labs.engineering.asu.edu/mps-lab/ml-accelerators/

Google Scholar URL

https://scholar.google.com/citations?user=SVft2R0AAAAJ

ORCID Profile ID

https://orcid.org/0000-0003-4262-3938

Research Interests

Shail's research develops agile design tools and techniques for efficient accelerator designs, including for dense/sparse tensor computations of Machine/Deep Learning models. These include compilation and mapping optimizations, execution cost modeling and bottleneck characterization, and explorations of hardware/software co-designs, including through systematic heuristics and machine learning. His research is regularly published in and referred by the top ACM/IEEE conferences and journals in these domains (design automation, embedded systems, and computer architecture) and has featured in premier forums (ARM Research Summits, NSF/Intel annual CAPA days, Future Chips Forum, etc.).

Shail's research interests and experience include:

Programmable Hardware Accelerators
Hardware/Software Co-Design
Agile and Sustainable Design Automation
Computer Architecture
Deep Learning and DNN Model Compression
Embedded and Cyber-physical Systems
Compiler Design and Optimizations
Execution Modeling and Bottleneck Characterization
High-Performance, Energy-efficient Computing
Near-Data Processing
Distributed, Real-time Edge Computing
Machine Learning for Systems

Research Group

Compiler Microarchitecture Lab/ Make Programming Simple Lab Center for Embedded Systems Affiliated with:School of Computing and Augmented Intelligence (SCAI),Ira A. Fulton Schools of Engineering, Arizona State University, Tempe, AZ.

Publications

Select Publications

[ASPLOS] Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis. Shail Dave, Tony Nowatzki, Aviral Shrivastava, in ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). (Won Silver Medal at ACM SIGBED Student Research Competition)
[Proceedings of the IEEE] Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights. Shail Dave, Riyadh Baghdadi, Tony Nowatzki, Sasikanth Avancha, Aviral Shrivastava, Baoxin Li. arXiv:2007.00864, 2020. [Paper] [summary tweet-thread]Key topics: Sources of sparsity in tensors; accelerator-aware pruning of deep learning models; implications of irregular or structured sparsity on hardware acceleration; analysis on sparsity-encoding schemes on storage; the impact of varying sparsity and tensor shapes of different DNN operations on data reuse; techniques for data extraction and load balancing of effectual (non-zero) computations; sparsity-aware dataflows; leveraging value similarity in tensors of computer vision and speech processing applications; trends and directions for accelerator/model codesigns.
[CODES+ISSS @ ESWEEK, TECS] dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators. Shail Dave, Youngbin Kim, Sasikanth Avancha, Kyoungwoo Lee, Aviral Shrivastava, in ACM Transactions on Embedded Computing Systems (TECS), Vol. 18, No. 5s, 2019 [Special Issue on ESWEEK 2019 - ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)] [Paper] [Slides with Demo] [Slides] [Poster] [Code] Key topics: Defining comprehensive hardware/software design space for loop nests; Accelerator cost model for evaluating execution metrics for variations in hardware architecture, dataflows, model layers, Search-space reduction techniques for getting efficient mappings in a few seconds; Generic algorithms for obtaining all unique data reuse scenarios for loop-orderings.
[DAC] RAMP: resource-aware mapping for CGRAs. Shail Dave, Mahesh Balasubramanian, and Aviral Shrivastava. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2018. [Paper] [Slides] [Poster] (Mapping Optimizations for Accelerating Loops of General-Purpose Computing).
[LATTE @ ASPLOS] Design Space Description Language for Automated and Comprehensive Exploration of Next-Gen Hardware Accelerators. Shail Dave and Aviral Shrivastava, in Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), co-located with ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2022. [Paper] [Talk] [Workshop] Key topics: Comprehensive, Reusable, Explainable, and Agile Design Exploration of Architectures.
[Demonstrations @ DATE, DAC] CCF: CGRA Compilation and Simulation Framework. Shail Dave, Aviral Shrivastava, in University Booth Demonstration at the 21st International Conference on Design Automation and Test in Europe (DATE), 2018 [Paper] [Infrastructure]

Other Publications

[DATE] Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level. Behnaz Ranjbar, Florian Klemme, Paul R. Genssler, Hussam Amrouch, Jinhyo Jung, Shail Dave, Hwisoo So, Kyongwoo Lee, Aviral Shrivastava, Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Francky Catthoor, Dwaipayan Biswas, Akash Kumar, in Proceedings of the 26th International Conference on Design Automation and Test in Europe (DATE), 2023. [Paper]
[VTS] Towards an Agile Design Methodology for Efficient, Secure, and Reliable ML Systems. Shail Dave, Alberto Marchisio, Muhammad Abdullah Hanif, Amira Guesmi, Aviral Shrivastava, Ihsen Alouani, Muhammad Shafique, in Proceedings of the 40th IEEE VLSI Test Symposium (VTS), 2022 (Invited Special Session). [Paper]
[TACO] SPX64: A Scratchpad Memory for General-Purpose Microprocessors. Abhishek Singh, Shail Dave, PanteA Zardoshti, Robert Brotzman, Chao Zhang, Xiaochen Guo, Aviral Shrivastava, Gang Tan, Michael Spear, in ACM Transactions on Architecture and Code Optimization (TACO), Vol. 18, No. 1, 2021 [Paper] [Talk @ HiPEAC '21]
[ICASSP] dMazeRunner: Optimizing Convolutions on Dataflow Accelerators. Shail Dave, Youngbin Kim, Sasikanth Avancha, Kyoungwoo Lee, Aviral Shrivastava, in 45th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2020). [Paper] [Slides] [Code] [Talk]
[DATE] URECA: A Compiler Solution to Manage Unified Register File for CGRAs. Shail Dave, Mahesh Balasubramanian, and Aviral Shrivastava.. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 1081-1086. IEEE, 2018. [Paper] [Slides]
[DATE] LASER: A hardware/software approach to accelerate complicated loops on CGRAs. Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, and Reiley Jeyapaul. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 1069-1074. IEEE, 2018. [Paper] [Slides]

Research Activity

SRC AI Hardware Program, Semiconductor Research Corporation
CAPA - NSF/Intel Joint Center on Computer Assisted Programming for Heterogeneous Architectures

Teaching Website URL

https://labs.engineering.asu.edu/mps-lab/cse420/

Courses

2021 Fall

Course Number	Course Title
CSE 420	Computer Architecture I

Presentations

Invited Lectures/Talks

Course Developed, CSE/CEN 598: Topics in Machine Learning Accelerator Design, Spring 2023 [class size: 28]
Guest Lectures and Tutorials on "working with Gem5 architectural simulator" and "implementations of microarchitecture components in Gem5 simulator", CSE 420: Computer Architecture I, Fall 2021 [class size: 57]
Guest Lecture on " Energy-efficient Acceleration of Residual Neural Nets onto Dataflow Accelerators", CSE 420: Computer Architecture I, Fall 2018 [class size: 115]
Guest Lecture on "Dataflow Accelerators", ASU 101: The ASU Experience, Fall 2018 [class size: 19]
Invited Talk on "Exploring Career Opportunities and Skill Enhancement" at sessions in International Student Orientation, ASU, Fall 2016 [total attendees: about 250]
Invited Talk and Panel Discussion on "Leadership and Involvement Opportunities and Skill Enhancement", organized by Graduate and Professional Students Association (GPSA) during International Student Orientation, Spring 2016 [attendees: about 20]

Other lectures/recitations during Teaching Assistantship (Fall 2016 – Spring 2018)

CSE 100: Principles of Programming with C++
CSE 330: Operating Systems
CSE 420/520: Computer Architecture (Outstanding TA Award)

Honors / Awards

Silver Medalist, ACM Student Research Competition (SRC), hosted by ACM SIGBED (Special Interest Group on Embedded Systems)
Completion Fellowship, Graduate College, Arizona State University – 2022-2023
Doctoral Fellowship, School of Computing, Informatics, Decisions, and Systems Engineering (CIDSE) – 2019, 2023
Outstanding Research Award, Graduate and Professional Students Association (GPSA), ASU – 2021-2022
Engineering Grad Fellowship, Ira A. Fulton Schools of Engineering, ASU – 2018, 2019, 2020, 2023
A. Richard Newton Young Student Fellowship – 53rd Annual Design Automation Conference (DAC), June 2016
Outstanding Computer Engineering TA Award, School of Computing, Informatics, Decisions and Systems Engineering (CIDSE), ASU – 2018
Team lead and core contributor, SRC AI hardware project @ ASU (AI for AI) (accepted, beginning 2023)
Student lead, ASU team, NSF/Intel joint research center for Computer Assisted Programming for Heterogeneous Architectures (CAPA). (Our group was among the total three hubs supported nationwide.)
NSF Workshop Panel on Sustainable Computing ("Architectures Track") - 2021-2022
Certificate of Appreciation (for outstanding service as social media chair), 17th ACM/IEEE Embedded Systems Week – 2021, 2022
Research Spotlight, IEEE Eta Kappa Nu (HKN) – 2022 [Coverage: IEEE Bridge Volume 118]
Invited for Inaugural Google Systems Innovation Summit – 2021 (Invitations limited to top global PhD students in computing systems.)
Research works regularly invited and featured in several premier events (ARM Research Summits, NSF/Intel CAPA Annual Days, Future Chips Forum, etc.)

Competitive Travel Grant Awards from:

School of Computing, Informatics, Decisions and Systems Engineering (CIDSE), ASU – 2018, 2019
Computer Engineering, ASU – Spring 2018
Graduate and Professional Student Association (GPSA), ASU – Summer 2016, Spring 2018, Fall 2019
Graduate College, ASU – 2019
ACM SIGDA and SIGBED – 2018, 2019
IEEE Computer Society Technical Committee on Parallel Processing (TCPP) – 2022

Professional Associations

Association for Computing Machinery (ACM)
Institute of Electrical and Electronics Engineers (IEEE)
New York Academy of Sciences
IEEE Computer Society
IEEE Eta Kappa Nu Honors Society
ACM Special Interest Group on Computer Architecture (SIGARCH)
ACM Special Interest Group on Embedded Systems (SIGBED)
IEEE Council on Design Automation (CEDA)
IEEE Technical Committee on Computer Architecture (TCCA)
Computer Architecture Student Association (CASA) (supported by: ACM SIGARCH / IEEE TCCA)

Graduate Faculties / Mentoring History

Mentor, Computer Architecture Long-Term Mentoring Program (CALM), Computer Architecture Student Association (CASA) - 2022-Present
Mentor, Meet a Senior Architect (MaSA), Computer Architecture Student Association (CASA) – 2022

Service

Conference Reviewer:

ACM Design Automation Conference (DAC) – 2018, 2019, 2020, 2022
IEEE International Conference on Design Automation and Test in Europe (DATE) – 2016, 2017
IEEE/ACM/IFIP International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS) – 2016, 2017
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) – 2019, 2023
IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) – 2019
IEEE Real-Time Systems Symposium (RTSS) – 2019
IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) – 2022
IEEE International Conference on Computer Design (ICCD) – 2019
International Conference on VLSI Design and Embedded Systems (VLSID & ES) – 2017, 2018

Program Committee Member:

Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), co-located with ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) – 2022, 2023

Journals Referee:

IEEE Transactions on Circuits and Systems I: Regular Papers – 2023
IEEE Sensors – 2022
ACM Transactions on Embedded Computing Systems (TECS) – 2017, 2019, 2020, 2022
ACM Transactions on Design Automation of Electronic Systems (TODAES) – 2020
IEEE Transactions on Multi-Scale Computing Systems (TMSCS) – 2016, 2017
International Journal on Design Automation for Embedded Systems, Springer – 2017

Select Voluntary, Organization, and Outreach Activities:

Social Media Chair, ACM/IEEE Embedded Systems Week – 2021, 2022. [LinkedIn] [Twitter]
Vice Chair, IEEE Eta Kappa Nu (HKN), ASU Chapter (2016–2017)
Invited Speaker, International Student Orientation, ASU – 2016, 2017
Webmaster, Compiler Microarchitecture Lab, 2017–2023
Invited Panelist on Early Career Panel, ASU 101: The ASU Experience, Fall 2018
Logistics management, Distinguished Speaker Invited Talks, CIDSE, ASU - 2017, 2018

Industry Positions

Software Engineer (Intern), The Mathworks, Natick, MA (Summer 2018) Research Group: Code Efficiency, Embedded Coder Project: Loop Optimizations for Target-Aware Code Generation.
ASIC Verification Engineer Intern, SanDisk Corporation, Milpitas, CA (Summer 2015) Project: Module-level verification of enterprise solid state drive controller ASIC.
Research Intern, Space Application Center, Indian Space Research Organization, India (Spring 2014) Project: End-to-end System Development for Precise Temperature Control of Cryogenic Cooler Systems of Next Generation Geostationary Satellites.

Executive Education Courses

Invited Talks:

NSF/Intel CAPA Annual days,NSF/Intel Joint Research Center for Computer Assisted Programming for Heterogeneous Architectures (CAPA) – 2018, 2019, 2020 (closed event) (Audience: NSF program managers, Intel researchers and fellows, researchers from top universities)
Future Chips Forum (3rd Annual Forum; Theme: “Reconfigurable Computing in Golden Age”), Beijing Innovation Center for Future Chips and the Institute of Microelectronics, Tsinghua University – 2018
ARM Research Summit, Cambridge, UK – 2018
Renegotiating the Levels of Abstraction for the Post Moore’s Law Era, Workshop at the Arm Research Summit, Austin, US – 2019
DAC-ROAD4NN: Annual International Workshop on Research Open Automatic Design for Neural Networks, co-located with the 59th Design Automation Conference (DAC 2022) – 2022 (usually 100s of attendees)
IBM AICS: IBM and IEEE CAS/EDS AI Compute Symposium (AICS) – 2022
Intel Labs Seminar (Virtual) – 2023
40th Annual IEEE VLSI Test Symposium (VTS) – 2022 Topic: "Towards an Agile Design Methodology for Efficient ML Systems"
MathWorks Research, Target-Aware Code Optimization and Generation (Host: Code Efficiency, Embedded Coder Group) – 2018
3rd Annual Secure RISC-V Workshop (SECRISCV), co-located with 18th ACM/IEEE Embedded Systems Week (ESWEEK) – 2022
HiPEAC: 16th International Conference on High-Performance Embedded Architectures and Compilers – 2021

Expertise Areas

Modeling and Simulation

Sustainability

Sustainable Development

Artificial Neural Networks

Machine Learning

Computational Modeling

Computer Architecture and Design

Computer Engineering

Cyberphysical and Embedded Systems