James Garvey

Director of Engineering, Advanced Cryptographic Solutions
General Dynamics, Mission Systems

Cryptographic technology for Space, Airborne and Ground applications. Advanced Infosec Machine (AIM) cryptographic processor, secure operating system, software development tools, cryptographic software and ASIC/FPGA design.

Director of Engineering, Trusted Space Solutions
General Dynamics, Mission Systems

High reliability space-borne payloads for Restricted National, GPS, Space Communication and Deep Space Transponder Programs. 

Sr. Tech. Manager, Digital Signal Processing Engineering, Mission Payloads
General Dynamics, Mission Systems

DSP algorithm and ASIC/FPGA development for Restricted National Programs, GPS, and Communication applications for high reliability space-based payloads.

Senior Technical Manager, ASIC/FPGA Design Center
General Dynamics, Mission Systems

DSP ASIC and FPGA devices for high reliability, space based and radiation tolerant applications.

Director of Design, Advanced Logic Division
ON Semiconductor

Engineering of the PureEdge PLL clock family and the GigaComm high-speed clock and data distribution family of devices.

Director of Engineering/Operations, Application Specific Products
Freescale Semiconductor Inc., Networking and Computing Systems Group (formerly Semiconductor Products Sector, Motorola)

Application-specific integrated circuit products for the networking market. Passive Optical Networking, Rapid IO, High-speed transceiver, and specialty networking technology development.

Research Manager, Semiconductor Systems Design Technology
Motorola, Semiconductor Products Sector, Sector Technology

Leadership of a design research organization with laboratories in Tempe Arizona, Geneva Switzerland and Munich Germany. Research and develop advanced design technology applied to large-scale digital systems in the areas of semicustom and low-power circuit design methods.

Engineering Manager, Design Tool Development
Motorola, Semiconductor Products Sector. ASIC Division

Development of specialized design tools for ASIC gate-array products. Mustang Automated Test Pattern Generation System, TrailBlazer Static Timing Analysis System, and the Decal Timing Calculation tool. U.S Patent for Bridging Fault Test Generation Methods, coinventor.

Intern/Engineer, Large Computer Products Division
Honeywell

Board and circuit test methods and tools. Test program generation tools; generated tests for over 200 devices. Developed a novel board integrity test system that utilized trace capacitance measurement for opens/short detection.