Viha Jaiswal
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Mail code: 5706Campus: Tempe
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Student Information
Graduate StudentComputer Engineering (Electrical Engineering)
Ira A Fulton Engineering
Viha Jaiswal is a graduate student in Computer Engineering (specializing in Electrical Engineering) at Arizona State University. With a strong foundation in Electronics and Communication Engineering, she graduated as the Valedictorian of her undergraduate class back in India. Her research and professional interests lie at the intersection of Hardware Architecture and Machine Learning, specifically focusing on FPGA Architecture, Digital Design, and Hardware Acceleration.
Currently, Viha serves as the Technical Chair for IEEE at ASU and Graduate Service Assistant. She brings diverse industry experience from roles at Deloitte and the Defense Research and Development Organization (DRDO).She is a passionate engineer who believes in practical learning.
- Jaiswal, V. (2024). Unveiling the Power of Infrared with Adaptive MSDE and MRCS: A Multi-Resolution Approach. DOI: 10.4108/eai.5-1-2024.2342546.
- Jaiswal, V. (2023). Bridging Gaps in Autism Care: The Smart Monitoring Solution. International Journal of Early Childhood Special Education (INT-JECSE)
- Adaptive MSDE and MRCS for Infrared Imaging: Proposed a novel multi-resolution architecture for image feature extraction. Validated efficiency in feature extraction and recognition through algorithmic optimization in MATLAB. (Published: DOI:10.4108/eai.5-1-2024.2342546).
- Deep Learning-Based Antenna Pattern Synthesis: Designed and simulated patch antennas using ANSYS HFSS to enhance radar-based target detection. Applied signal processing principles to FPGA-based ML acceleration, improving detection accuracy by 18%.
- Smart Monitoring Solutions for Autism Care: Developed a smart monitoring system providing real-time feedback to caregivers and personalized learning support. (Published in International Journal of Early Childhood Special Education).