Sarma Vrudhula

Professor,

School of Computing and Augmented Intelligence

CTRPT 203-25 Tempe, AZ 85281
Mail code: 8809

Campus: Tempe
‌

Long Bio

Sarma Vrudhula is a professor in the School of Computing and Augmented Intelligence at Arizona State University. He received a bachelor's degree in mathematics from the University of Waterloo, Ontario, Canada, in 1976, majoring in computer science and mathematical statistics. He moved to Venice CA in 1977 and while enrolled as a graduate student at in EE-Systems department at the University of Southern California, worked as a research assistant in USC Information Sciences Institute in Marina Del Rey, CA. He received his master's and doctoral degrees in electrical engineering from the University of Southern California in 1980 and 1985, respectively.

During 1985-1992, he was on the faculty of the EE-Systems department of the University of Southern California. From 1992 to 2005, he was a professor in the Electrical and Computer Engineering department at the University of Arizona. During that period, he was the founding director of the NSF UA/ASU Center for Low Power Electronics. He joined ASU in 2005, and became the director for the Center for Embedded Systems at ASU in 2006, which became an NSF IUCRC Center in 2009. He became a fellow of the IEEE for “contributions to low power and energy-efficient design of digital circuits and systems.”

His work spans several areas in design automation and computer-aided design for digital integrated circuit and systems, focusing on energy management of circuits and systems. Specific topics include: energy optimization of battery powered computing systems and wireless sensor networks; system level dynamic power and thermal management of multicore processors and system-on-chip (SoC); statistical methods for the analysis of process variations; statistical optimization of performance, power and leakage; new circuit architectures of threshold logic circuits for the design of ASICs and FPGAs; technology mapping with threshold logic circuits; the implementation of threshold logic using spintronic devices, and non-Boolean computation in emerging technologies. His teaching experience includes both undergraduate and graduate courses in digital systems design and testing, VLSI design, CAD algorithms for VLSI, advanced synthesis and verification methods, computer architecture, and discrete mathematics.

Education

Ph.D. Electrical Engineering, University of Southern California 1985
M.S. Electrical Engineering, University of Southern California in 1980
Bachelor's degree. Mathematics (Computer Science and Mathematical Statistics) University of Waterloo, Canada 1976

Curriculum Vitae

Google Scholar URL

https://scholar.google.com/citations?user=2UF8gNsAAAAJ&hl=en

Publications

Sarvesh Bhardwaj, Sarma Vrudhula. Leakage minimization of digital circuits using gate sizing in the presence of process variations. IEEE Transactions on Computer-Aided Design (2008).
A. Goel, S. Vrudhula. Current source based cell models for statistical timing and signal integrity analysis. In Proceedings of the IEEE/ACM Design Automation Conference (DAC), (Anaheim, CA), (2008).
Goel, Amit, Vrudhula, Sarma. Current source based standard cell model for accurate signal integrity and timing analysis. (2008).
Goel, Amit, Vrudhula, Sarma, Taraporevala, Feroze, Ghanta, Praveen. Best Paper Award on A Methodology for Characterization of Large Macro Cells and IP Blocks Considering process variations. (2008).
Gowda, Tejaswi, Leshner, Sam, Vrudhula, Sarma, Kim, Seungchan. Threshold Logic Gene Regulatory Model: Prediction of dorsal-ventral patterning and hardware-based simulation of Drosophila. Springer (2008).
Gowda, Tejaswi, Vrudhula, Sarma. A decomposition based approach for synthesis of multi-level threshold logic circuits. (2008).
Gowds, Tejaswi, Leshner, Samuel, Vrudhula, Sarma, Kim, Seungchan. Threshold logic gene regulatory model: Prediction of dorsal-ventral patterning and hardware based simulation of Drosophila. (2008).
Kannan, Deepa, Shrivastava, Aviral, Bhardwaj, Sarvesh, Vrudhula, Sarma. Power reduction of functional units considering temperature and process variations. (2008).
Kannan, Deepa, Shrivastava, Aviral, Bhardwaj, Sarvesh, Vrudhula, Sarma. Temperature and Process Variations aware Power Gating of Functional Units. (2008).
Berezowski, Krzysztof, Vrudhula, Sarma. Multiple-Valued Logic Circuits using Negative Differential Devices. (2007).
Bhardwaj, Sarvesh, Ghanta, Praveen, Vrudhula, Sarma. A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations. (2007).
Goel, Amit, Bhardwaj, Sarvesh, Ghanta, Praveen, Vrudhula, Sarma. Computation of joint timing yield for sequential networks considering process variations. (2007).
Gowda, Tejaswi, Leshner, Samuel, Vrudhula, Sarma, Konjevod, Goran. Synthesis of threshold logic circuits using tree matching. (2007).
Gowda, Tejaswi, Leshner, Samuel, Vrudhula, Sarma, Konjevod, Goran. Synthesis of Threshold Logic using Tree Matching. (2007).
Gowda, Tejaswi, Vrudhula, Sarma, Kim, Seungchan. Threshold Logic Gene Regulatory Networks. IEEE (2007).
Gowda, Tejaswi, Vrudhula, Sarma, Konjevod, Goran. A non-ILP based threshold logic systhesis methodology. (2007).
Gowda, Tejaswi, Vrudhula, Sarma, Konjevod, Goran. Combinational Equivalence Checking for Threshold Circuits. (2007).
Gowda, Tejaswi, Vrudhula, Sarma, Konjevod, Goran. Combinational equivalence checking for threshold logic circuits. ACM (2007).
Gowds, Tejaswi, Leshner, Samuel, Vrudhula, Sarma, Kim, Seungchan. Threshold logic gene regulatory networks. (2007).
Rao, Ravishankar, Vrudhula, Sarma. Performance optimal processor throttling under thermal constraints. (2007).
Rao, Ravishankar, Vrudhula, Sarma, Chakrabarti, Chaitali. Throughput of multi-core processors under thermal constraints. (2007).
Wang, Wenping, Yang, Shengqi, Bhardwaj, Sarvesh, Vattikonda, Rakesh, Vrudhula, Sarma, Liu, Frank, Cao, Yu. The impact of NBTI on the performance of combinational and sequential circuits. (2007).
Bhardwaj, Sarvesh, Cao, Yu, Vrudhula, Sarma. Statistical Leakage Minimization through Joint Selection of Gate Sizes, Gate Lengths and Threshold Voltage. (2006).
Bhardwaj, Sarvesh, Ghanta, Praveen, Vrudhula, Sarma. A framework for statistical timing analysis using non-linear delay and slew models. (2006).
Bhardwaj, Sarvesh, Vrudhula, Sarma, Cao, Yu. LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. (2006).
Bhardwaj, Sarvesh, Vrudhula, Sarma, Ghanta, Praveen, Cao, Kevin. Modeling of Intra-die Process Variations for Accurate Analysis and Optimization of Nano-scale Circuits. (2006).
Cho, Youngjin, Chang, Naehyuck, Vrudhula, Sarma, Chakrabarti, Chaitali. High-Level Power Management of Embedded Systems with Application Specific Energy Cost Functions. (2006).
Ghanta, Praveen, Vrudhula, Sarma. Variational Interconnect Delay Metrics for Statistical Timing Analysis. (2006).
Ghanta, Praveen, Vrudhula, Sarma, Bhardwaj, Sarvesh, Panda, Rajendran. Stochastic Variational Analysis of Large Power Grids Considering Intradie Correlations. (2006).
Rao, Ravishankar, Vrudhula, Sarma, Chakrabarti, Chaitali, Chang, Naehyuck. An optimal analytical solution for processor speed control with thermal constraints. (2006).
Wang, Wenping, Bhardwaj, Sarvesh, Vattikonda, Rakesh, Cao, Devin, Vrudhula, Sarma. Predictive Modeling of the NBTI effect for reliable design. (2006).
Zhuo, Jianli, Chang, Naehyuck, Chakrabarti, Chaitali, Vrudhula, Sarma. Extending the lifetime of fuel cell based hybrid systems. (2006).
Berezowski, Krzysztof, Vrudhula, Sarma. Automatic Design of Binary Multiple-Valued Logic Gates on the RTD Series. (2005).
Bhardwaj, Sarvesh, Vrudhula, Sarma. Formalizing designer's preferences for multiattribute optimization with applications to leakage-delay tradeoffs. (2005).
Bhardwaj, Sarvesh, Vrudhula, Sarma. Leakage minimization of nanoscale circuits in the presence of systemic and random variations. (2005).
Ghanta, Praveen, Bhardwaj, Sarvesh, Vrudhula, Sarma. Variational analysis of interconnects and power grids considering process variations. (2005).
Ghanta, Praveen, Vrudhula, Sarma, Panda, Rajendran, Wang, Janet. Stochastic Power Grid Analysis Considering Process Variations. (2005).
Rao, Ravishankar, Vrudhula, Sarma. Energy Optimal Speed Control of Devices with Discrete Speed Sets. (2005).
Rao, Ravishankar, Vrudhula, Sarma, Chang, Naehyuck. Battery optimization vs energy optimization: Which to choose and when?. (2005).
Shu, Tao, Krunz, Marwan, Vrudhula, Sarma. Power Balanced coverage time optimization for clustered wireless sensor networks. (2005).
Chopra, Kaviraj, Vrudhula, Sarma. Implicit Pseudo Boolean Enumeration Algorithms for Input Vector Control. (2004).
Chopra, Kaviraj, Vrudhula, Sarma, Bhardwaj, Sarvesh. Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. (2004).
Dasika, Sridhar, Vrudhula, Sarma, Chopra, Kaviraj. A Framework for Battery Aware Sensor Management. (2004).
Raj, Sreeja, Vrudhula, Sarma, Wang, Janet. Statistical Gate Sizing to Minimize Timing Yield Loss. (2004).
Rao, Ravishankar, Vrudhula, Sarma. Disk Drive Energy Optimization for Audio-Visual Applications. (2004).
Rao, Ravishankar, Vrudhula, Sarma. Energy Optimization for a Two Device Dataflow Chain. (2004).
Sreeramaneni, Raghukiran, Vrudhula, Sarma. Energy Profiler for Hardware/Software Codesign. (2004).
Vrudhula, Sarma, Raj, Sreeja, Wang, Janet. A Methodology for Improving Timing Yield in the Presence of Process Variations. (2004).
wang, janet, Ghanta, Praveen, Vrudhula, Sarma. Stochastic analysis of interconnect performance in the presence of process variations. (2004).
Daler Rakhmatov, Sarma Vrudhula. Energy Management for Battery-Powered Embedded Systems. ACM Transactions on Embedded Computing Systems (2003).
Daler Rakhmatov, Sarma Vrudhula, Deborah Wallach. A Model for Battery Lifetime Analysis for Organizing Applications on a Pocket Computer. IEEE Transactions on VLSI Systems (2003).
Vrudhula, Sarma B K, Schroder, D. Proceedings of the NSF S/IUCRC Symposium. (2003).
Agarwal, Aseem, Blaauw, David, Zolotov, Vladimir, Vrudhula, Sarma. Computation and Refinement of Statistical Bounds on Circuit Delay. (2003).
Agarwal, Aseem, Blaauw, David, Zolotov, Vladimir, Vrudhula, Sarma. Statistical Timing Analysis Using Bounds. (2003).
Bhardwaj, Sarvesh, Vrudhula, Sarma, Blaauw, David. Large $ au$AU: Timing Analysis under Uncertainity. (2003).
Rao, Ravishankar, Vrudhula, Sarma, Rakhmatov, Daler. Analysis of Discharge Techniques for Multiple Battery Systems. (2003).
Agarwal, Aseem, Blaauw, David, Zolotov, Vladimir, Vrudhula, Sarma. Statistical Timing Analysis using Bounds and Selective Enumeration. (2002).
Bhardwaj, Sarvesh, Vrudhula, Sarma, Blaauw, David. Estimation of Signal Arrival Times in the presence of Delay Noise. (2002).
Rakhmatov, Daler, Vrudhula, Sarma. Hardware-Software Bipartitioning for Dynamically Reconfigurable Systems. (2002).
Rakhmatov, Daler, Vrudhula, Sarma, Chakrabarti, Chaitali. Battery-Conscious Task Sequencing for Portable Devices Including Voltage/Clock Scaling. (2002).
Rakhmatov, Daler, Vrudhula, Sarma, Wallach, Deborah. Battery Lifetime Prediction for Energy-Aware Computing. (2002).
Vrudhula, Sarma, Blaauw, David, Sirichotiyakul, Supamas. Estimation of the Likelihood of Capactive Coupling Noise. (2002).
Zareba, Gregorz, Paulusinski, Olek, Vrudhula, Sarma, Allee, David, Mensch, William. Analysis, Implementation and Testing of An Analog-To-Digital Over Sampling Converter in A Field Programmable Analog Array. (2002).
Rakhmatov, Daler, Vrudhula, Sarma. A Analytical High-Level Battery Model for use in Energy Management of Portable Electronic Systems. (2001).
Rakhmatov, Daler, Vrudhula, Sarma. Minimizing Routing Configuration Cost in Dynamically Reconfigurable FPGA's. (2001).
Rakhmatov, Daler, Vrudhula, Sarma. Time-to-Failure Estimation for batteries in Portable Electronic Systems. (2001).
Wang, Haibo, Vrudhula, Sarma, Palusinski, Olek. Performance Driven Placement and Routing for Field Programmable Analog Arrays. (2001).
Zareba, Gregorz, Paulusinski, Olek, Warecki, Sylvester, Vrudhula, Sarma. Data Communication and Control in Mixed-Signal Development System. (2001).
Wang, Haibo, Vrudhula, Sarma, Palusinski, Olek. Behavioral Level Analog Synthesis for Field Programmable Analog Arrays. (2000).
Warecki, Sylvester, Palusinski, Olek, Vrudhula, Sarma, Mensch, William. Analog Digital Development Board for Rapid Prototyping Mixed Signal Circuits. (2000).
Pandey, Amit, Ramadurai, Vinod, Mangudi, Ajay, Gebreyesus, Martin, Vrudhula, Sarma, Palusinski, Olek. Performance Comparison of Filters Implemented in Field Programmable Gate Arrays and Field Programmable Analog Arrays. (1999).
Reider, Carl, Znamirowski, Lech, Palusinski, Olek, Vrudhula, Sarma, Rakhmatov, Daler. Dynamically Reconfigurable Analog/Digital Hardware Implementation using FPGA and FPAA Technologies. (1999).
Wang, Qi, Vrudhula, Sarma. A New Short Circuit Power Model for Complex CMOS Gates. (1999).
Wang, Qi, Vrudhula, Sarma. An Investigation of Power-Delay Tradeoffs for Dual AA$V_T$ CMOS Circuits. (1999).
Wang, Qi, Vrudhula, Sarma. Data Driven Power Optimization of Sequetial Circuits. (1998).
Wang, Qi, Vrudhula, Sarma. Efficient Procedures for Minimizing the Standby Power in Dual $V_T$ CMOS Circuits. (1998).
wang, Qi, Vrudhula, Sarma. On Short Circuit Power Estimation of CMOS Inverters. (1998).
Wang, Qi, Vrudhula, Sarma. Static Power Optimization of Deep Submicron CMOS Circuits for Dual $V T$ Technology. (1998).
McCarley, Kendel, Vrudhula, Sarma. Macro Instruction Generation for Dynamic Logic Caching. (1997).
Tsun, Edwin, Vrudhula, Sarma. Rapid Prototyping of Asynchronous Multiple Function Unit Network. (1997).
Wang, Haibo, Vrudhula, Sarma. A Low-Voltage, low-Power Ring Pointer for Use in a FIFO Memory. (1997).
Wang, Qi, Vrudhula, Sarma. Optimization of Sequential Circuits Without Global Resets by Structural Transformations. (1997).
Wang, Qi, Vrudhula, Sarma, Ganguly, Shantanu. An Investigation of Power Delay Trade-offs Using Logic and Structural Transformations: Experiments On the PowerPC. (1997).
Wang, Qi, Vrudhula, Sarma. Multi-Level Optimization for Low Power using Local Logic Transformations. (1996).
Mackey, Richard, Rodriguez, Jeffery, Vrudhula, Sarma, Carothers, Jodale. A single-Chip Asynchronous Echo Canceller for high-Speed Data Communications. (1995).
Vrudhula, Sarma, Lai, Yung-Te, Pedram, Massoud. Efficient Computation of the Probability and Reed-Muller Spectra of Boolean Functions using Edge-Valued Binary Decision Diagrams. (1995).
Vrudhula, Sarma, Xie, Hong-Yu. Techniques for CMOS Power Estimation and Logic Synthesis for Low Power. (1994).
Ho, King, Vrudhula, Sarma. A New Algorithm for Two Dimensional Multiple Folding. (1993).
Lai, Yung-Te, Pan, Kao, Pedram, Massoud, Vrudhula, Sarma. FGMap: A Technology Mapping Algorithm for Look-Up Table Type FPGAs based on Function Graphs. (1993).
Lai, Yung-Te, Pedram, Massoud, Vrudhula, Sarma. BDD Based Logic Decomposition with Applications to FPGA Synthesis. (1993).
Lai, Yung-Te, Pedram, Massoud, Vrudhula, Sarma. FGLIP: An Integer Linear Program Solver Based on Function Graphs. (1993).
Majumdar, Amitava, Vrudhula, Sarma. Statistical Analysis of Controllability. (1993).
Vrudhula, Sarma, Majumdar, Amitava. Models for Estimating Test Length and Fault Coverage in Random Testing. (1993).
Lai, Yung-Te, Vrudhula, Sarma. An Efficient Matching Algorithm using BDDs for Logic Verification. (1992).
Lai, Yung-Te, Vrudhula, Sarma. Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification. (1992).
Lai, Yung-Te, Vrudhula, Sarma, Pedram, Massoud. Boolean Matching using Binary Decision Diagrams with Applications to Logic Synthesis and Verification. (1992).
Majumdar, Amitava, Vrudhula, Sarma. Distribution and Moments of Test Length. (1992).
Majumdar, Amitava, Vrudhula, Sarma. On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. (1992).
Abdullah, A, Vrudhula, Sarma. Topological Via Minimization and Routing. (1991).
Ho, King, Vrudhula, Sarma. Flexible Transistor Matrix (FTM). (1991).
Lai, Yung-Te, Vrudhula, Sarma. HINTS: A Hardware Interpretation System. (1991).
Vrudhula, Sarma, Majumdar, Amitava. A Branching Process Model for Observability Analysis of Combinational Circuits. (1991).
Vrudhula, Sarma, Majumdar, Amitava. A Stochastic Model for Fault Propagation in Combinational Circuits. (1991).
Ambler, A.P., Abadir, M., Vrudhula, Sarma B K. Economics of Design and Test for Electronic Circuits and Systems. (1990).
Kurdahi, Fadi, Vrudhula, Sarma. Characterization of Wire Length Distributions for Standard Cell Layouts. (1990).
Ravikumar, Chennagiri, Vrudhula, Sarma. Parallel Algorithms for Coloring Perfect Graphs with Applications to VLSI Layout and Synthesis. (1990).
Vrudhula, Sarma, Majumdar, Amitava. Stochastic Models for Testing of Combinational Circuits. (1990).
Ravikumar, Chennagiri, Vrudhula, Sarma. A Parallel Algorithm for Coloring Interval Graphs with Applications to Gate Matrix Layout and Register Allocation. (1989).
Ravikumar, Chennagiri, Vrudhula, Sarma. A Parallel Approach to Three Layer Channel Routing. (1989).
Ravikumar, Chennagiri, Vrudhula, Sarma. LARA: A Layout Accelerator Based on Reduced Array Architecture. (1989).
Ravikumar, Chennagiri, Vrudhula, Sarma. Parallel Placement on Hypercube Architecture. (1989).
Vrudhula, Sarma, Pi, J. An Investigation into Statistical Properties of Partitioning and Placement Problems. (1989).
Ravikumar, Chennagiri, Vrudhula, Sarma. Parallel Placement on Reduced Array Architecture. (1988).
Ravikumar, Chennagiri, Vrudhula, Sarma, Patnaik, Lalit. A Data Parallel Approach to Local Search Placement Algorithms. (1988).
Kumar, Viktor Prasanna, Vrudhula, Sarma. A General Purpose VLSI Array for Efficient Signal and Image processing. (1987).
Vrudhula, Sarma, Breuer, Melvin. Analysis of BIST Techniques for CMOS Stuck-Open Faults. (1987).
Vrudhula, Sarma, Parker, Alice. On the Relation between Wire Length Distributions and Placement of Logic on Master Slice ICs. (1984).
Vrudhula, Sarma, Klein, Steve. PLATES: A Metric-Free VLSI Layout Language. (1982).
Vrudhula, Sarma, Parker, Alice. The Complexity of Two-Dimensional Compaction of VLSI Layouts. (1982).
Klein, Steve, Vrudhula, Sarma. Parameterized Modules and Interconnections in Unified Hardware Descriptions. (1981).

Research Activity

Vrudhula,Sarma B K*, Seo,Jae-Sun. "IUCRC FRP: Collaborative Research: Scalable and PowerEfficient Compressive Sensing CMOS Image Sensors and Reconstruction Circuits". NSF-IIP(10/1/2015 - 9/30/2017).
Kitchen,Jennifer Nisha*, Vrudhula,Sarma B K. CES Project: Radhard Ka-Band Power Amplifiers for Space. CES CONSORTIUM(8/1/2015 - 8/31/2016).
Vrudhula,Sarma B K*, Cao,Yu, He,Jingrui, Seo,Jae-Sun. Design of Low-Power Hardware Accelerator for Bio-Signal Processing Project. SAMSUNG ELECTRONICS(7/1/2015 - 3/1/2016).
Vrudhula,Sarma B K*. IUCRC FRP: Collaborative Research: Testability and timing analysis in nanoscale designs in the presence of process variations. NSF-CISE-IIS(9/15/2014 - 8/31/2016).
Vrudhula,Sarma B K*. I UCRC: Consortium for Embedded Systems - Phase II. NSF-IIP(4/15/2014 - 3/31/2019).
Vrudhula,Sarma B K*. Novel Circuit Architectures and Design Methodologies for Low Power Digital Systems. NSF-ENG(9/1/2012 - 8/31/2016).
Vrudhula,Sarma B K*, Fainekos,Georgios E.. REU: Collaborative Research: Consortium for Embedded Systems. NSF-ENG(8/10/2012 - 2/28/2015).
Vrudhula,Sarma B K*. IUCRC: Collaborative Research: Synthesis and Design of Robust Threshold Logic Circuits. NSF-ENG(8/1/2012 - 7/31/2015).
Vrudhula,Sarma B K*. Membership Agreement: CES Member: Marvell Semiconductor, Inc.: Consortium for Embedded Systems Membership. (7/13/2011 - 8/31/2014).
Vrudhula,Sarma B K*. CES Member: Toyota Motor Engineering - Manufacturing NA Inc. Toyota Tech. Center(6/21/2010 - 8/15/2012).
Vrudhula,Sarma B K*. CES Member: QualComm Inc. QualComm(1/1/2010 - 12/31/2012).
Vrudhula,Sarma B K*. CES Member: Intel Corporation. INTEL CORP(9/28/2009 - 9/27/2012).
Vrudhula,Sarma B K*. NeTS: Medium: Collaborative Research: Exploiting Battery-Supply Nonlinearities in Optimal Resource Mgmt and Protocol Design for Wireless Sensor. NSF-CISE(8/1/2009 - 7/31/2013).
Vrudhula,Sarma B K*, Chatha,Karamvir Singh, Lee,Yann-Hang, Shrivastava,Aviral. Collaborative Research: Consortium for Embedded Systems. NSF-ENG(3/1/2009 - 2/28/2015).
Vrudhula,Sarma B K*. A Novel Threshold Logic Based Circut Architecture for High Performance and Low Power Digital Systems. SFAz(10/1/2008 - 1/31/2011).
Vrudhula,Sarma B K*, Chatha,Karamvir Singh, Dasgupta,Partha, Shrivastava,Aviral. An Integrated Design Framework for Application Development on Multi-core Processors. SFAz(5/16/2008 - 7/31/2012).
Vrudhula,Sarma B K*. CES Member: Raytheon Company: Consortium for Embedded Systems Membership. RAYTHEON(1/1/2008 - 8/31/2012).
Vrudhula,Sarma B K*. Collaborative Research: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold Logic. NSF-ENG(10/1/2007 - 9/30/2011).
Vrudhula,Sarma B K*. VOID wc 11/8/07. NSF-ENG(10/1/2007 - 10/2/2007).
Gupta,Sandeep Kumar S*, Dasgupta,Partha, Stanzione Jr,Daniel Charles, Vrudhula,Sarma B K. CAA: Building Greener Datacenters in Arizona. SFAz(3/30/2007 - 9/30/2008).
Vrudhula,Sarma B K*. Collaborative Research: Consortium for Embedded Systems. NSF-ENG(3/15/2007 - 2/29/2008).
Vrudhula,Sarma B K*. ASU CLPE-Industry. UNIV OF AZ(9/1/2005 - 12/30/2008).
Chakrabarti,Chaitali*, Chatha,Karamvir Singh, Chatha,Karamvir Singh, Vrudhula,Sarma B K, Vrudhula,Sarma B K. CSR-EHS: Analytical Techniques for Global Energy Minimizaiton of a System of Interacting Components. NSF-CISE(8/1/2005 - 5/31/2010).
Vrudhula,Sarma B K*. Low Power Electronics - State (AZ Dept of Commerce): Dr. Naehyuck Chang SOW Continuation of DWS0088. UNIV OF AZ(4/1/2005 - 6/30/2007).
Chakrabarti,Chaitali*, Chatha,Karamvir Singh, Vrudhula,Sarma B K. Power Optimization Techniques for a System of Interacting Heterogenous Components. CEIT(1/3/2005 - 6/30/2009).
Vrudhula,Sarma B K*. ITR: Methodologies for Robust Design of Information Systems Under Multiple Sources of Uncertainty. UNIV OF MICHIGAN(1/1/2005 - 7/30/2008).

Courses

2025 Summer

Course Number	Course Title
CEN 795	Continuing Registration

2025 Spring

Course Number	Course Title
CSE 493	Honors Thesis
CEN 792	Research
CEN 795	Continuing Registration
CSE 499	Individualized Instruction
CEN 503	Algo for Comp-Aided Desn of Di
EEE 503	Algo for Comp-Aided Desn of Di

2024 Fall

Course Number	Course Title
CSE 493	Honors Thesis
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
CSE 590	Reading and Conference
CSE 580	Practicum
CSE 790	Reading and Conference
CEN 792	Research
CEN 580	Practicum
CEN 799	Dissertation
CEN 795	Continuing Registration

2024 Summer

Course Number	Course Title
CEN 584	Internship
CEN 795	Continuing Registration
CEN 795	Continuing Registration

2024 Spring

Course Number	Course Title
CSE 493	Honors Thesis
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
CSE 590	Reading and Conference
CSE 790	Reading and Conference
CEN 790	Reading and Conference
CEN 599	Thesis
CEN 580	Practicum
CSE 580	Practicum
CSE 599	Thesis
CSE 580	Practicum
CEN 792	Research
CEN 799	Dissertation
CEN 590	Reading and Conference
CEN 795	Continuing Registration
CSE 492	Honors Directed Study
CEN 690	Reading and Conference
CEN 792	Research
CEN 790	Reading and Conference

2023 Fall

Course Number	Course Title
CSE 493	Honors Thesis
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
CSE 590	Reading and Conference
CSE 580	Practicum
CSE 790	Reading and Conference
CEN 792	Research
CEN 599	Thesis
CSE 492	Honors Directed Study
CEN 584	Internship
CEN 580	Practicum
CEN 790	Reading and Conference
CEN 590	Reading and Conference
CEN 799	Dissertation
CEN 795	Continuing Registration
CSE 120	Digital Design Fundamentals
CSE 120	Digital Design Fundamentals

2023 Summer

Course Number	Course Title
CEN 584	Internship
CEN 795	Continuing Registration

2023 Spring

Course Number	Course Title
CSE 320	Design/Syn Digital Hardware
CSE 493	Honors Thesis
CSE 492	Honors Directed Study
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
CSE 590	Reading and Conference
CSE 790	Reading and Conference
CSE 595	Continuing Registration
CEN 790	Reading and Conference
CEN 599	Thesis
CEN 580	Practicum
CSE 580	Practicum
CSE 599	Thesis
CSE 580	Practicum
CEN 792	Research
CEN 799	Dissertation
CEN 590	Reading and Conference
CEN 795	Continuing Registration
CSE 320	Design/Syn Digital Hardware
CSE 320	Design/Syn Digital Hardware
CEN 690	Reading and Conference
CEN 792	Research
CEN 790	Reading and Conference

2022 Fall

Course Number	Course Title
CSE 320	Design/Syn Digital Hardware
CSE 493	Honors Thesis
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
CSE 590	Reading and Conference
CSE 580	Practicum
CSE 790	Reading and Conference
CEN 792	Research
CEN 599	Thesis
CEN 584	Internship
CEN 580	Practicum
CEN 790	Reading and Conference
CEN 590	Reading and Conference
CEN 799	Dissertation
CSE 320	Design/Syn Digital Hardware
CSE 320	Design/Syn Digital Hardware
CEN 795	Continuing Registration

2022 Summer

Course Number	Course Title
CEN 584	Internship
CEN 795	Continuing Registration

2022 Spring

Course Number	Course Title
CSE 493	Honors Thesis
CSE 492	Honors Directed Study
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
EEE 599	Thesis
CSE 590	Reading and Conference
CSE 790	Reading and Conference
CSE 595	Continuing Registration
CEN 790	Reading and Conference
CEN 599	Thesis
CEN 580	Practicum
CSE 580	Practicum
CSE 599	Thesis
CSE 580	Practicum
CEN 792	Research
CEN 799	Dissertation
CEN 590	Reading and Conference
CEN 795	Continuing Registration
CSE 492	Honors Directed Study
CSE 493	Honors Thesis
CEN 503	Algo for Comp-Aided Desn of Di
CEN 792	Research
CEN 790	Reading and Conference

2021 Fall

Course Number	Course Title
CSE 320	Design/Syn Digital Hardware
CSE 493	Honors Thesis
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
CSE 590	Reading and Conference
CSE 580	Practicum
CSE 790	Reading and Conference
CEN 792	Research
CEN 599	Thesis
CEN 584	Internship
CEN 580	Practicum
CEN 790	Reading and Conference
CEN 590	Reading and Conference
CEN 799	Dissertation
CSE 320	Design/Syn Digital Hardware
CSE 320	Design/Syn Digital Hardware
CEN 795	Continuing Registration
CSE 599	Thesis

2021 Summer

Course Number	Course Title
CEN 584	Internship
CEN 795	Continuing Registration

2021 Spring

Course Number	Course Title
EEE 790	Reading and Conference
EEE 592	Research
EEE 493	Honors Thesis
EEE 499	Individualized Instruction
EEE 690	Reading and Conference
EEE 595	Continuing Registration
EEE 492	Honors Directed Study
CSE 493	Honors Thesis
CSE 492	Honors Directed Study
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
EEE 599	Thesis
EEE 792	Research
EEE 799	Dissertation
EEE 595	Continuing Registration
CSE 590	Reading and Conference
CSE 790	Reading and Conference
CSE 595	Continuing Registration
EEE 590	Reading and Conference
CEN 790	Reading and Conference
EEE 795	Continuing Registration
CEN 599	Thesis
CEN 580	Practicum
CSE 580	Practicum
CSE 599	Thesis
CSE 790	Reading and Conference
CSE 580	Practicum
CEN 792	Research
CEN 580	Practicum
CEN 799	Dissertation
CEN 590	Reading and Conference
CEN 795	Continuing Registration
EEE 492	Honors Directed Study
CSE 493	Honors Thesis
EEE 493	Honors Thesis
EEE 499	Individualized Instruction
CSE 590	Reading and Conference
CSE 230	Computer Org/Assemb Lang Prog
EEE 230	Computer Org/Assemb Lang Prog

2020 Fall

Course Number	Course Title
CSE 320	Design/Syn Digital Hardware
CSE 493	Honors Thesis
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
CSE 590	Reading and Conference
CSE 580	Practicum
CSE 790	Reading and Conference
CEN 792	Research
CEN 599	Thesis
CEN 584	Internship
CEN 580	Practicum
CEN 790	Reading and Conference
CEN 590	Reading and Conference
CEN 799	Dissertation
CSE 320	Design/Syn Digital Hardware
CSE 320	Design/Syn Digital Hardware
CSE 320	Design/Syn Digital Hardware
CEN 795	Continuing Registration

2020 Summer

Course Number	Course Title
EEE 690	Reading and Conference
EEE 590	Reading and Conference
EEE 790	Reading and Conference
CEN 584	Internship
EEE 592	Research
EEE 595	Continuing Registration
EEE 599	Thesis
EEE 792	Research
EEE 795	Continuing Registration
EEE 799	Dissertation
EEE 590	Reading and Conference

2020 Spring

Course Number	Course Title
EEE 790	Reading and Conference
EEE 592	Research
EEE 493	Honors Thesis
EEE 499	Individualized Instruction
EEE 690	Reading and Conference
EEE 595	Continuing Registration
EEE 492	Honors Directed Study
CSE 493	Honors Thesis
CSE 492	Honors Directed Study
CSE 595	Continuing Registration
CSE 599	Thesis
CSE 792	Research
CSE 795	Continuing Registration
CSE 799	Dissertation
EEE 599	Thesis
EEE 792	Research
EEE 799	Dissertation
EEE 595	Continuing Registration
CSE 590	Reading and Conference
CSE 790	Reading and Conference
CSE 595	Continuing Registration
EEE 590	Reading and Conference
CEN 790	Reading and Conference
EEE 795	Continuing Registration
CEN 599	Thesis
CEN 580	Practicum
CSE 580	Practicum
CSE 599	Thesis
CSE 790	Reading and Conference
CSE 580	Practicum
CEN 792	Research
CEN 799	Dissertation
CEN 590	Reading and Conference
CEN 795	Continuing Registration
EEE 492	Honors Directed Study
CSE 493	Honors Thesis
EEE 493	Honors Thesis
CEN 590	Reading and Conference
EEE 499	Individualized Instruction

Presentations

Gowda, Tejaswi, Vrudhula, Sarma, Kim, Seungchan. Modeling of Gene Regulatory Networks Using Threshold Logic. DREAM2 Workshop (Dec 2007).
Vrudhula, Sarma. A Unified Approach to Statistical Analysis of Full-Chip Leakage and Timing in the presence of Process Variations. 3rd CLEAN Workshop (Sep 2007).
Vrudhula, Sarma. Performance optimization of single and multi-core processors under Performance optimization of single and multi-core processors under thermal constraints. (Sep 2007).
Vrudhula, Sarma. Performance optimization of single and multi-core processors under thermal constraints. (Sep 2007).
Gowda, Tejaswi, Leshner, Samuel, Vrudhula, Sarma, Kim, Seungchan. Threshold Logic Gene Regulatory Networks. GENSIPS 2007 (Jun 2007).
Vrudhula, Sarma. Robust design of nano-scale circuits in the presence of process variations,. IEEE, International Conference on VLSI Design (Jan 2007).
Vrudhula, Sarma. Optimization in the presence of process variations. (Dec 2006).
Vrudhula, Sarma. Source & Impact of Process Variations. (Dec 2006).
Vrudhula, Sarma. Statistical Models of Interconnects & Gates. (Dec 2006).
Vrudhula, Sarma. Statistical Timing & Leakage Analysis. (Dec 2006).
Vrudhula, Sarma. Deterministic Static Timing Analysis. (Dec 2006).
Vrudhula, Sarma. Stochastic Analysis of interconnects and power grids in the presence of process variations. First International Workshop on Interconnect Design and Variability (Dec 2006).
Vrudhula, Sarma. VLSI Circuit. (Dec 2006).
Vrudhula, Sarma. Methodology for the robust design of nano-scale circuits in the presence of process variations. (May 2006).
Vrudhula, Sarma. Statistical timing and leakage analysis in the presence of process variations. (May 2006).
Vrudhula, Sarma. Energy Management in Battery Powered Embedded Systems. (Mar 2004).
Vrudhula, Sarma. Statistical Gate Sizing to Improve Timing Yield. (Feb 2004).
Vrudhula, Sarma. Analysis and Optimization of Power and Performance of Digital Circuits and Systems. (Feb 2004).
Vrudhula, Sarma. Statistical Approach to Signal Integrity and Performance Analysis of DSM CMOS Circuits. (Jan 2004).
Vrudhula, Sarma. Identification of the Minimum Leakage States. (Oct 2003).
Vrudhula, Sarma. Statistical Gate Sizing to Improve Timing Yield. (Oct 2003).
Vrudhula, Sarma. Battery-Aware Design of Portable Embedded Systems. (Aug 2003).
Vrudhula, Sarma. Energy Management in Battery Powered Embedded Systems. (Jun 2003).
Vrudhula, Sarma. Approaches to Minimizing Subthreshold Leakage. (Jun 2003).
Vrudhula, Sarma. Probabilistic Analysis of Interconnect Coupling Noise in Deep Submicron Circuits. (Oct 2001).
Vrudhula, Sarma. Probabilistic Analysis of Interconnect Coupling Noise in Deep Submicron Circuits. (Aug 2001).
Vrudhula, Sarma. Probabilistic Analysis of Interconnect Coupling Noise in Deep Submicron Circuits. (Jun 2001).
Vrudhula, Sarma. Algorithms for Minimizing Standby Power in Dual VT CMOS Circuits. (Aug 2000).
Vrudhula, Sarma. Algorithms for Minimizing Standby Power in Dual VT CMOS Circuits. (Jun 2000).
Vrudhula, Sarma. Algorithms for Minimizing Standby Power in Dual VT CMOS Circuits. (Apr 2000).
Vrudhula, Sarma. Algorithms for Minimizing Standby Power in Dual VT CMOS Circuits. (Sep 1999).
Vrudhula, Sarma. Dynamically Reconfigurable Architectures: Opportunities and Challenges,. Chair) International Conference on Computer Design (ICCD) (Oct 1998).
Vrudhula, Sarma. Rewiring of Combinational and Sequential Logic for Low Power, Department of Electrical Engineering. (Sep 1997).
Vrudhula, Sarma. Center for Low Power Electronics. (Jun 1997).
Vrudhula, Sarma. Power Optimization of Combinational and Sequential Logic Circuits. (Jun 1997).
Vrudhula, Sarma. Techniques for Power Reduction in Combinational and Sequential Logic Circuits. (May 1997).
Vrudhula, Sarma. Lowe Power Electronics: Digital Circuits. Hughes Low Power/Low Voltage Symposium (Mar 1997).
Vrudhula, Sarma. Register Transfer Level Testing using Edge Valued Binary Decision Diagrams. (Oct 1996).
Vrudhula, Sarma. Edge Valued Binary Decision Diagrams with Applications to Logic Verification, Synthesis, Spectral Transforms, and Cominatorial Optimization. (May 1995).
Vrudhula, Sarma. Edge Valued Binary Decision Diagrams with Applications to Logic Verification, Synthesis, Spectral Transforms, and Cominatorial Optimization. (Apr 1995).
Vrudhula, Sarma. A Fast and Accurate Technique for Estimating Signal Activity in CMOS Logic Circuits. (Feb 1995).
Vrudhula, Sarma. A synchronous Systems Design Methodology. (Feb 1995).
Vrudhula, Sarma. Edge Valued Binary Decision Diagrams. International Dahsthul Seminar on Computer-Aided Design and Test (Feb 1995).
Vrudhula, Sarma. Low Power Design at the Logic, Register-Transfer & Behavioral Levels. (Apr 1994).
Vrudhula, Sarma. Synthesis of Asynchronous Systems from Data Flow Specifications. (Nov 1993).
Vrudhula, Sarma. Synthesis of Asynchronous Systems from Data Flow Specifications. (Aug 1993).
Vrudhula, Sarma. Design and Test for VLSI. (Dec 1992).
Vrudhula, Sarma. Modelling Fault Propagation for Predicting Fault Coverage and Test Length. (Dec 1992).
Vrudhula, Sarma. Stochastic Models for Testability Analysis of Digital Circuits. (Apr 1992).
Vrudhula, Sarma. Stochastic Models in Testing of Digital Circuits. MCC (Sep 1990).
Vrudhula, Sarma. Testability Analysis and Characterization of Digital Circuits. (Mar 1990).
Vrudhula, Sarma. LARA: A Layout Accelerator Based on the Reduced Array Architecture. (Aug 1988).
Vrudhula, Sarma. Statistical Properties of Partitioning and Floorplanning Problems. (Aug 1988).
Vrudhula, Sarma. Minority Fellowship Awards in Science for Undergraduates. (Oct 1987).
Vrudhula, Sarma. VLSI Design Automation and Testing. (Apr 1987).
Vrudhula, Sarma. On Mapping Algorithms to Linear and Fault Tolerant Systolic Arrays. IEEE International Conference on Computer Design (Oct 1986).
Vrudhula, Sarma. Wireability Analysis of Integrated Circuits. (Dec 1985).
Vrudhula, Sarma. A Metric-Free VLSI Layout Language. (Aug 1982).
Vrudhula, Sarma. A Branching Process Model for Fault Propagation in Combinational Circuits. Pacific Northwest Test Workshop
Vrudhula, Sarma. Synthesis Algorithms for Low Power Digital Systems.

Service

ACM, Associate Editor (2006 - 2009)
IEEE, Associate Editor (2006 - 2009)
CES Director of Research, Consortium for Embedded Systems, Chair (2005 - 2008)
CSE Faculty Recruiting Committee, Chair (2005 - 2008)
Graduate Program Committee, Committee Member (2006 - 2008)
ASU Senate, Committee Member (2005 - 2008)
Computer Engineering Planning, (2006 - 2007)
Personnel Committee, Committee Member (2006 - 2007)
New Faculty Mentors, Mentor (2006 - 2007)
IEEE/ACM, Chair - Technical Program Committee (Power) (2005 - 2006)
RDIC - International, Chair - Technical Program Committee (2005 - 2006)
Program Committee Member (2003 - 2006)
IEEE, Program Committee Member (2005 - 2005)
IEEE/ACM- Design Automation Conference, Organizer & Chair of Special Session (2005 - 2005)
ECE Department Faculty Status (Promotion & Tenure) Committee, Member (2002 - 2004)
IEEE/ACM, Program Committee Member (2001 - 2004)
Summer Internship Program (SPIN) for CLPE,, Director (1996 - 2004)
Sensor Networks and Communication Systems, Session Chair (2003 - 2003)
UA ECE Faculty Recruiting Committee, Chair (2000 - 2003)
Computer Engineering Program, External Reviewer (2002 - 2002)
Studia Informaticia, Member of Editorial Board (2001 - 2002)
Program Committee Member (2001 - 2001)
Program Committee Member (1999 - 1999)
National Science Foundation S/IUCRC Symposium, Chair (1999 - 1999)
Vice Chair (1998 - 1998)
Computer Systems Support Solutions, Member of the Board of Directors (1998 - 1998)
IEEE International, Organizer & Session Chair (1998 - 1998)
IEEE International, Track Chair (1998 - 1998)
IEEE, Associate Editor (1996 - 1998)
NSF S/IUCRC, Program Committee Member (1997 - 1997)
UA ECE Faculty Recruiting Committee, (1997 - 1997)
Computer Engineering Curriculum, Committee Member (1996 - 1997)
Computer Engineering Faculty Recruiting Subcommittee, Committee Member (1996 - 1997)
Undergraduate Curriculum Committee, Committee Member (1996 - 1997)
Peer Evaluation Committee, Committee Member (1995 - 1997)
Program Committee Member (1993 - 1997)
International Graduate Admissions, Committee Member (1994 - 1996)
Computer Policy Committee, Chair (1993 - 1996)
Computer Engineering Faculty Recruiting Subcommittee, (1993 - 1994)
Second International Workshop, General Chairman (1993 - 1993)
VLSI/VHSIC, Session Chair (1993 - 1993)
Computer Engineering Curriculum, Committee Member (1992 - 1993)
ACM, Reviewing & Refereeing (Present)
IEE Proceedings, Reviewing & Refereeing (Present)
IEEE, Reviewing & Refereeing (Present)
Invited External Reviewer for the Portuguese National Science Foundation, Reviewing & Refereeing (Present)
Journal of Electronic Testing and Test Applications, Reviewing & Refereeing (Present)
Journal of Integrated Computer-Aided Engineering, Reviewing & Refereeing (Present)
Proposals for the National Science Foundation, Reviewing & Refereeing (Present)